/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2020. All rights reserved.
 * Author: Yang Jianbo <yangjianbo1@huawei.com>
 * Generated on: 2020/2/06
 * Function description: adaptation header file related to the PCIe main chip
 */

#ifndef PCIE_CHIP_H
#define PCIE_CHIP_H
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mbus.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/kallsyms.h>
#include <linux/slab.h>
#include <linux/msi.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/hardirq.h>
#include <asm/irq.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>

#include <asm/mach/pci.h>
#include <asm/delay.h>
#include <asm/memory.h>
#include <asm/cacheflush.h>

#include "hw_drv_core.h"
#include "pcie_board_attr.h"

#define AGEING_LOOPBACK_CHECK_FILE  "/mnt/jffs2/aging/pcieflag"
#define AGEING_LOOPBACK_RESULT_FILE "/mnt/jffs2/aging/pcieresult"
#define AGEING_LOOPBACK_TEST_SIZE   (1024)
#define AGEING_RESULT_SUCC          (0)
#define AGEING_RESULT_FAIL          (1)
#define AGEING_RESULT_NOCHECK       (2)

#define PCIE_SYS_BASE_PHYS         (0x10100000) /* SYSCTRL */
#define PCIE0_BASE_ADDR_PHYS       (0x40000000) /* MEM space */
#define PCIE1_BASE_ADDR_PHYS       (0x58000000) /* MEM space */
#define PCIE0_MEMIO_BASE           (0x50000000) /* cfg space */
#define PCIE1_MEMIO_BASE           (0x68000000) /* cfg space */
#define PCIE_BASE_ADDR_SIZE        (0x1000000)
#define PCIE_BASE_ADDR_SIZE_MXL    (0x2601000)
#define PCIE_BASE_ADDR_SIZE_1152   (0x2800000)
#define PCIE_BASE_ADDR_SIZE_LSW    PCIE_BASE_ADDR_SIZE
#define PCIE_BASE_ADDR_SIZE_COMMON PCIE_BASE_ADDR_SIZE
#define PCIE_MEM_SPACE_SIZE        (0xa00000)
#define PCIE_MEM_SPACE_SIZE_MXL    (0x2001000)
#define PCIE_MEM_SPACE_SIZE_1152   (0x1040000)
#define PCIE_MEM_SPACE_SIZE_LSW    (0x10200000)
#define PCIE_MEM_SPACE_SIZE_COMMON PCIE_MEM_SPACE_SIZE
#define PCIE_BAR2_BUS_ADDR_OFFSET  (PCIE_MEM_SPACE_SIZE_1152)

/* pcie 0 */
#define PCIE0_CFG_REGION0_SIZE     (0x7FFFFFF)
#define PCIE0_CFG_REGION0_BASE     (PCIE0_MEMIO_BASE)
#define PCIE0_CFG_REGION0_LIMIT    (PCIE0_CFG_REGION0_BASE + PCIE0_CFG_REGION0_SIZE)
#define PCIE0_CFG_REGION0_TAR      (0)

#define PCIE0_MEM_REGION1_SIZE     (0xC37FFF)
#define PCIE0_MEM_REGION1_BASE     (PCIE0_BASE_ADDR_PHYS)
#define PCIE0_MEM_REGION1_LIMIT    (PCIE0_MEM_REGION1_BASE + PCIE0_MEM_REGION1_SIZE)

#define PCIE0_MEM_REGION2_SIZE     (0x3FFF)
#define PCIE0_MEM_REGION2_BASE     (PCIE0_BASE_ADDR_PHYS + \
	PCIE_MEM_SPACE_SIZE_1152 - PCIE0_MEM_REGION2_SIZE - 1)
#define PCIE0_MEM_REGION2_LIMIT    (PCIE0_BASE_ADDR_PHYS + PCIE_MEM_SPACE_SIZE_1152 - 1)
#define PCIE0_MEM_REGION2_TAR_BASE (PCIE0_BASE_ADDR_PHYS + PCIE_BAR2_BUS_ADDR_OFFSET)

/* pcie 1 */
#define PCIE1_CFG_REGION0_SIZE     (0x7FFFFFF)
#define PCIE1_CFG_REGION0_BASE     (PCIE1_MEMIO_BASE)
#define PCIE1_CFG_REGION0_LIMIT    (PCIE1_CFG_REGION0_BASE + PCIE1_CFG_REGION0_SIZE)
#define PCIE1_CFG_REGION0_TAR      (0)

#define PCIE1_MEM_REGION1_SIZE     (0xC37FFF)
#define PCIE1_MEM_REGION1_BASE     (PCIE1_BASE_ADDR_PHYS)
#define PCIE1_MEM_REGION1_LIMIT    (PCIE1_MEM_REGION1_BASE + PCIE1_MEM_REGION1_SIZE)

#define PCIE1_MEM_REGION2_SIZE     (0x3FFF)
#define PCIE1_MEM_REGION2_BASE     (PCIE1_BASE_ADDR_PHYS + \
	PCIE_MEM_SPACE_SIZE_1152 - PCIE1_MEM_REGION2_SIZE - 1)
#define PCIE1_MEM_REGION2_LIMIT    (PCIE1_BASE_ADDR_PHYS + PCIE_MEM_SPACE_SIZE_1152 - 1)
#define PCIE1_MEM_REGION2_TAR_BASE (PCIE1_BASE_ADDR_PHYS + PCIE_BAR2_BUS_ADDR_OFFSET)
#define SC_PERCTRL38               (0x134)

#define USB_PCIE_COM_PHY_SLE_REG   (0x1011C820)
#define USB_PCIE_COM_PHY_SLE_MASK  (0x3)

/* 5182T cfg space */
#define PCIE0_BASE_ADDR_PHYS_5182T      (0x40000000) /* MEM space */
#define PCIE1_BASE_ADDR_PHYS_5182T      (0x60000000) /* MEM space */
#define PCIE2_BASE_ADDR_PHYS_5182T      (0x20000000) /* MEM space */
#define PCIE3_BASE_ADDR_PHYS_5182T      (0x30000000) /* MEM space */
#define PCIE0_MEMIO_BASE_5182T          (0x5F000000) /* cfg space */
#define PCIE1_MEMIO_BASE_5182T          (0x67000000) /* cfg space */
#define PCIE2_MEMIO_BASE_5182T          (0x2F000000) /* cfg space */
#define PCIE3_MEMIO_BASE_5182T          (0x3F000000) /* cfg space */

/* pcie 0 */
#define PCIE0_CFG_REGION0_SIZE_5182T        (0xFFFFFF)
#define PCIE0_CFG_REGION0_BASE_5182T        (PCIE0_MEMIO_BASE_5182T)
#define PCIE0_CFG_REGION0_LIMIT_5182T \
	(PCIE0_CFG_REGION0_BASE_5182T + PCIE0_CFG_REGION0_SIZE_5182T)
#define PCIE0_IATU0_LOWER_TARGET_REG_5182T  (0x1000000)

#define PCIE0_MEM_REGION1_SIZE_5182T        (0xFF)
#define PCIE0_MEM_REGION1_BASE_5182T        (PCIE0_BASE_ADDR_PHYS_5182T + 0x1000000)
#define PCIE0_MEM_REGION1_LIMIT_5182T \
	(PCIE0_MEM_REGION1_BASE_5182T + PCIE0_MEM_REGION1_SIZE_5182T)
#define PCIE0_IATU1_LOWER_TARGET_REG_5182T  PCIE0_MEM_REGION1_BASE_5182T

#define PCIE0_MEM_REGION2_SIZE_5182T        (0xFFFFFF)
#define PCIE0_MEM_REGION2_BASE_5182T        (PCIE0_BASE_ADDR_PHYS_5182T)
#define PCIE0_MEM_REGION2_LIMIT_5182T \
	(PCIE0_BASE_ADDR_PHYS_5182T + PCIE0_MEM_REGION2_SIZE_5182T)
#define PCIE0_IATU2_LOWER_TARGET_REG_5182T  PCIE0_MEM_REGION2_BASE_5182T

/* pcie 1 */
#define PCIE1_CFG_REGION0_SIZE_5182T        (0xFFFFFF)
#define PCIE1_CFG_REGION0_BASE_5182T        (PCIE1_MEMIO_BASE_5182T)
#define PCIE1_CFG_REGION0_LIMIT_5182T \
	(PCIE1_CFG_REGION0_BASE_5182T + PCIE1_CFG_REGION0_SIZE_5182T)
#define PCIE1_IATU0_LOWER_TARGET_REG_5182T  (0x1000000)

#define PCIE1_MEM_REGION1_SIZE_5182T        (0xFF)
#define PCIE1_MEM_REGION1_BASE_5182T        (PCIE1_BASE_ADDR_PHYS_5182T + 0x1000000)
#define PCIE1_MEM_REGION1_LIMIT_5182T \
	(PCIE1_MEM_REGION1_BASE_5182T + PCIE1_MEM_REGION1_SIZE_5182T)
#define PCIE1_IATU1_LOWER_TARGET_REG_5182T  PCIE1_MEM_REGION1_BASE_5182T

#define PCIE1_MEM_REGION2_SIZE_5182T        (0xFFFFFF)
#define PCIE1_MEM_REGION2_BASE_5182T        (PCIE1_BASE_ADDR_PHYS_5182T)
#define PCIE1_MEM_REGION2_LIMIT_5182T \
	(PCIE1_BASE_ADDR_PHYS_5182T + PCIE1_MEM_REGION2_SIZE_5182T)
#define PCIE1_IATU2_LOWER_TARGET_REG_5182T  PCIE1_MEM_REGION2_BASE_5182T

/* pcie 2 */
#define PCIE2_CFG_REGION0_SIZE_5182T        (0xFFFFFF)
#define PCIE2_CFG_REGION0_BASE_5182T        (PCIE2_MEMIO_BASE_5182T)
#define PCIE2_CFG_REGION0_LIMIT_5182T \
	(PCIE2_CFG_REGION0_BASE_5182T + PCIE2_CFG_REGION0_SIZE_5182T)
#define PCIE2_IATU0_LOWER_TARGET_REG_5182T  (0x1000000)

#define PCIE2_MEM_REGION1_SIZE_5182T        (0xFF)
#define PCIE2_MEM_REGION1_BASE_5182T        (PCIE2_BASE_ADDR_PHYS_5182T + 0x1000000)
#define PCIE2_MEM_REGION1_LIMIT_5182T \
	(PCIE2_MEM_REGION1_BASE_5182T + PCIE2_MEM_REGION1_SIZE_5182T)
#define PCIE2_IATU1_LOWER_TARGET_REG_5182T  PCIE2_MEM_REGION1_BASE_5182T

#define PCIE2_MEM_REGION2_SIZE_5182T        (0xFFFFFF)
#define PCIE2_MEM_REGION2_BASE_5182T        (PCIE2_BASE_ADDR_PHYS_5182T)
#define PCIE2_MEM_REGION2_LIMIT_5182T \
	(PCIE2_BASE_ADDR_PHYS_5182T + PCIE2_MEM_REGION2_SIZE_5182T)
#define PCIE2_IATU2_LOWER_TARGET_REG_5182T  PCIE2_MEM_REGION2_BASE_5182T

/* 5182T IATU table reg definition change */
#define PCIE_IATU_CFG_BASE_5182T                            (0x4000)
#define PCIE_IATU_CFG_INBOUND_OFFSET                        (0x100)
#define PCIE_IATU_CFG_REGION_CTRL1(_channel_)               ((_channel_) * 0x200 + 0x00)
#define PCIE_IATU_CFG_REGION_CTRL2(_channel_)               ((_channel_) * 0x200 + 0x04)
#define PCIE_IATU_CFG_REGION_LOWER_BASE_ADDR(_channel_)     ((_channel_) * 0x200 + 0x08)
#define PCIE_IATU_CFG_REGION_UPPER_BASE_ADDR(_channel_)     ((_channel_) * 0x200 + 0x0C)
#define PCIE_IATU_CFG_REGION_LIMIT_ADDR(_channel_)          ((_channel_) * 0x200 + 0x10)
#define PCIE_IATU_CFG_REGION_LOWER_TRGT_ADDR(_channel_)     ((_channel_) * 0x200 + 0x14)
#define PCIE_IATU_CFG_REGION_UPPER_TRGT_ADDR(_channel_)     ((_channel_) * 0x200 + 0x18)

/* 1156 addr space not divide Memory and Config, manually alloc 16MB as cfg space
 * 0x6000_0000 ~ 0x703F_FFFF 260MB
 */
#define PCIE_MEM_SPACE_SIZE_1156     (0x1000000)
/* MEM */
#define PCIE_FST_N_MEM_BASE_1156     (0x60000000) /* MEM base addr */
#define PCIE_FST_N_MEM_LIMIT_1156    (PCIE_FST_N_MEM_BASE_1156 + PCIE_MEM_SPACE_SIZE_1156 - 1)

/* CFG */
#define PCIE_FST_N_MEM_SIZE_1156     (0xF400000)  /* 244MB MEM space */
#define PCIE_FST_N_CFG_BASE_1156     (PCIE_FST_N_MEM_BASE_1156 + PCIE_FST_N_MEM_SIZE_1156)
#define PCIE_FST_N_CFG_SIZE_1156     (0x1000000)  /* 16MB cfg space */
#define PCIE_FST_N_CFG_LIMIT_1156    (PCIE_FST_N_CFG_BASE_1156 + PCIE_FST_N_CFG_SIZE_1156 - 1)
#define PCIE_FST_N_CFG_LOWER_1156    (0x1000000)

/* in 244MB MEM space, only 10MB for MEM space, subsequent 256B for IO space */
/* IO */
#define PCIE_FST_N_IO_BASE_1156      (PCIE_FST_N_MEM_BASE_1156 + PCIE_MEM_SPACE_SIZE_1156)
#define PCIE_IO_SPACE_SIZE           (0x100)
#define PCIE_FST_N_IO_LIMIT_1156     (PCIE_FST_N_IO_BASE_1156 + PCIE_IO_SPACE_SIZE - 1)

#define PCIE_FST_N_DBI_SIZE_1156     (0x1000)
#define PCIE_FST_N_DBI_BASE_1156     (0x11900000)

/* 0x1000 misc cfg + 0x2000 pcs cfg + 0x2000 iatu cfg + 0x2000 edma cfg */
#define PCIE_FST_N_MISC_SIZE_1156    (0x7000)
#define PCIE_FST_N_MISC_BASE_1156    (0x11901000)
#define PCIE_CFG_SPACE_SIZE_1156     (0x1000)

/* pcie_iatu table para offset */
#define IATU_VIEWPORT_OFFSET       (0x900)
#define IATU_REGION_CTRL1_OFFSET   (0x904)
#define IATU_REGION_CTRL2_OFFSET   (0x908)
#define IATU_LBAR_OFFSET           (0x90C)
#define IATU_UBAR_OFFSET           (0x910)
#define IATU_LAR_OFFSET            (0x914)
#define IATU_LTAR_OFFSET           (0x918)
#define IATU_UTAR_OFFSET           (0x91C)

/* pcie_iatu controller reg 1 */
#define PCIE0_IATU0_REGION_CTRL_REG1   (0x4)
#define PCIE0_IATU1_REGION_CTRL_REG1   (0x0)
#define PCIE0_IATU2_REGION_CTRL_REG1   (0x5)
#define PCIE1_IATU0_REGION_CTRL_REG1   (0x4)
#define PCIE1_IATU1_REGION_CTRL_REG1   (0x2)
#define PCIE1_IATU2_REGION_CTRL_REG1   (0x0)

/* pcie controller type */
#define PCIE_IATU_TYPE_CFG0     (0x4)
#define PCIE_IATU_TYPE_IO       (0x2)
#define PCIE_IATU_TYPE_MEM      (0x0)

/* pcie_iatu controller reg 2 */
#define PCIE0_IATU_REGION_CTRL_REG2    (0x90000000)
#define PCIE_IATU_REGION_CTRL_REG2     (0x80000000)

#define PCIE0_IATU0_LOWER_TARGET_REG   (0x01000000)
#define PCIE0_IATU1_LOWER_TARGET_REG   (0x40000000)
#define PCIE0_IATU2_LOWER_TARGET_REG   (0x00200000)
#define PCIE1_IATU0_LOWER_TARGET_REG   (0x01000000)
#define PCIE1_IATU1_LOWER_TARGET_REG   (0x58a00000)
#define PCIE1_IATU2_LOWER_TARGET_REG   (0x58000000)
#define PCIE1_IATU3_EXTLSW_LOWER_TARGET_REG   (0x50000000)

#define DBI_BASE_ADDR                  (0x10160000)
#define DBI_BASE_ADDR_5182T            (0x10120000)
#define DBI_SPACE_SIZE                 (0x1000)
#define MISC_BASE_ADDR                 (0x10161000)
#define MISC_BASE_ADDR_5182T           (0x10121000)
#define MISC_SPACE_SIZE                (0x3000)
#define PCIE_CTRL_SIZE                 (DBI_SPACE_SIZE + MISC_SPACE_SIZE)

/* pcie1 module base addr offset */
#define PCIE1_BASE_REG_OFFSET          (0x4000)

/* 82T chip pcie module base addr offset */
#define PCIE1_BASE_REG_OFFSET_5182T    (0x10000)
#define PCIE2_BASE_REG_OFFSET_5182T    (0x20000)

/* DBI space reg offset */
#define DBI_CMD_STATUS_OFFSET          (0x4)
#define DBI_PORT_LINK_CTRL_OFFSET      (0x710)
#define DBI_DEBUG_REG0_OFFSET          (0x728)

#define DBI_SPACE_ENABLE               (0x100007)

#define DBI_BASE_ADDR_0                (0x10A00000) /* IO space 64k */
#define DBI_BASE_ADDR_1                (0x10A02000) /* IO space 64k */
#define ECS_TZPC_BASE                  (0x10101000) /* TZPC space 4k */

#define PCIE_APP_LTSSM_ENABLE          (11)

#define PCIE_PHY_VALUE0                (0x05605001)
#define PCIE_PHY_VALUE1                (0x20050006)

#define PCIE_CTRL_RST_1156_REG         (0x1191b40c)
#define PCIE_CTRL_RST_1156_MSK         (0x7)
#define PCIE_CTRL_CLK_1156_REG         (0x1191b20c)
#define PCIE_CTRL_CLK_1156_MSK         (0x7F)
#define PCIE_CTRL_CLK_PHY_1156_REG     (0x1191b210)
#define PCIE_CTRL_CLK_PHY_1156_MSK     (0x3)
#define PCIE_CTRL_REFCLK_CTRL_REG      (0x1191b810)
#define PCIE_CTRL_REFCLK_CTRL_MSK      (0x1)
#define PCIE_CTRL_UPSPHY_RST_REG       (0x1191b410)
#define PCIE_CTRL_UPSPHY_RST_MSK       (0x7)

/* pcie reg bit counts */
#define PCIE_BIT_0  (0)
#define PCIE_BIT_1  (1)
#define PCIE_BIT_2  (2)
#define PCIE_BIT_3  (3)
#define PCIE_BIT_4  (4)
#define PCIE_BIT_5  (5)
#define PCIE_BIT_6  (6)
#define PCIE_BIT_7  (7)
#define PCIE_BIT_8  (8)
#define PCIE_BIT_9  (9)
#define PCIE_BIT_10 (10)
#define PCIE_BIT_11 (11)
#define PCIE_BIT_12 (12)
#define PCIE_BIT_13 (13)
#define PCIE_BIT_14 (14)
#define PCIE_BIT_15 (15)
#define PCIE_BIT_16 (16)
#define PCIE_BIT_17 (17)
#define PCIE_BIT_18 (18)
#define PCIE_BIT_19 (19)
#define PCIE_BIT_21 (21)
#define PCIE_BIT_22 (22)
#define PCIE_BIT_23 (23)
#define PCIE_BIT_24 (24)
#define PCIE_BIT_25 (25)
#define PCIE_BIT_26 (26)
#define PCIE_BIT_27 (27)
#define PCIE_BIT_28 (28)
#define PCIE_BIT_29 (29)
#define PCIE_BIT_30 (30)
#define PCIE_BIT_31 (31)

#define PCIE_BIT_MASK(b)   (1UL << (b))

/* definition of chip reg base addr and range */
#define SYSCTRL_BASE_ADDR              (0x10100000) /* base addr of the system control reg */
#define CRG_DIO_BASE_ADDR              (0x14880000) /* base addr of the system clk gating reg */
/* virtual addr range of the PCIE misc reg mapping */
#define PCIE_MISC_BASE_SIZE            (0x1000)
/* virtual addr range of the PCIE dbi reg mapping */
#define PCIE_DBI_BASE_SIZE             (0x1000)
#define PCIE_OLD_MISC_BASE_ADDR        (0x10100000) /* base addr of old chip misc reg */
#define PCIE_OLD_MISC_BASE_SIZE        (0x1000)     /* range of old chip misc reg */
/* offset of pcie controller 12, controls PCIE_TX_SWING */
#define PCIE_COMBOPHY12_ADDR           (0x1030)
#define PCIE0_MODE_SEL                 (0x1)        /* pcie0 select mask */
#define PCIE1_MODE_SEL                 (0x2)        /* pcie1 select mask */
#define PCIE2_MODE_SEL                 (0x4)        /* pcie2 select mask */
#define PCIE_LINK_TRY_MAX_5115         (10)         /* max times of SD5115 chip try link */
/* max times of try link for SD5116 and newer ones */
#define PCIE_LINK_TRY_MAX_5116         (100)
#define PCIE_LINK_UP_STABLE            (3)          /* PCIE link setup threshold */

#define PCIE_APP_LTSSM_ENABLE          (11)

#define PCIE_INVALID_INT8              (0xFF)
#define PCIE_INVALID_INT32             (0xFFFFFFFF)
#define PCIE_MODEL_UNRESET_REG_5115    (0x10100130)
#define PCIE_MODEL_UNRESET_5115        (0x01800000)

/*
 * SD511x series chips, chip alloc PCIE space addr, information in chip user guide
 * 0x4000_0000~0x4FFF_FFFF    256MByte    PCIE0 Memory addr (peer EP space)
 * 0x5000_0000~0x57FF_FFFF    128MByte    PCIE0 Config addr (peer EP space)
 * 0x5800_0000~0x67FF_FFFF    256MByte    PCIE1 Memory addr (peer EP space)
 * 0x6800_0000~0x6FFF_FFFF    128MByte    PCIE1 Config addr (peer EP space)
 */
#define PCIE0_BASE_CFG_ADDR            (0x50000000) /* PCIE0 CFG space base addr */
#define PCIE0_BASE_CFG_SIZE            (0x400000)   /* PCIE0 CFG range of space mapping */
#define PCIE1_BASE_CFG_ADDR            (0x68000000) /* PCIE1 CFG space base addr */
#define PCIE1_BASE_CFG_SIZE            (0x1000)     /* PCIE1 CFG range of space mapping  */
/* PCIE2 CFG range of space mapping (5182T support) */
#define PCIE2_BASE_CFG_SIZE            (0x1000)
#define PCIE0_BASE_MEM_ADDR            (0x40000000) /* PCIE0 MEM space base addr */
#define PCIE0_BASE_MEM_SIZE            (0x1100000)  /* PCIE0 MEM range of space mapping  */
#define PCIE1_BASE_MEM_ADDR            (0x58000000) /* PCIE1 MEM space base addr */
#define PCIE1_BASE_MEM_SIZE            (0x1100000)  /* PCIE1 MEM range of space mapping  */
#define PCIE_BASE_IO_SIZE              (0x1000000)  /* io space size */

#define TRY_MAX_LOOPBACK_DETECT        (10)         /* max times of loopback detection */
#define PCIE_LOOPBACK_STATUS_MASK      (0x3f)       /* loopback status mask */
#define PCIE_LOOPBACK_STATUS_VALUE     (0x1b)       /* loopback satus value */
#define PCIE_LOOPBACK_UDELAY_10US      (10)         /* loopback of delay 10ns */
#define PCIE_LOOPBACK_BUFFER_ADDR_MASK (0xfffff000) /* loopback buffer addr mask */
#define PCIE_LOOPBACK_LTAR_OFFSET      (0x1000)     /* loopback ltar offset */
#define PCIE_LOOPBACK_PER_DATA_LEN     (0x4)        /* loopback test space init size */

#define PCIE_TEST_DATA_LEN             (8192) /* pcie loopback test space size */
#define PCIE_TEST_DATA_HALF_LEN        ((PCIE_TEST_DATA_LEN) / 2)
#define PCIE_TEST_OPT_DISABLE          (0) /* PCIE looback test operate type, close */
#define PCIE_TEST_OPT_ENABLE           (1) /* PCIE looback test operate type, enable */
#define PCIE_TEST_OPT_START            (2) /* PCIE looback test operate type, start */
#define PCIE_TEST_OPT_RESULT           (3) /* PCIE looback test operate type, get result */

#define PERI_PCIE0_5115              (0xBC)
#define PERI_PCIE1_5115              (0xC0)
#define PERI_PCIE6_5115              (0xd4)
#define PERI_PCIE7_5115              (0xd8)
#define PERI_PCIE8_5115              (0xDC)
#define PERI_PCIE9_5115              (0xE0)
#define PERI_PCIE10_5115             (0x1C)
#define PERI_PCIE11_5115             (0x2C)

#define PERI_PCIE0_5116              (0x00)
#define PERI_PCIE1_5116              (0x04)
#define PERI_PCIE6_5116              (0x18)
#define PERI_PCIE7_5116              (0x1c)
#define PERI_PCIE8_5116              (0x20)
#define PERI_PCIE9_5116              (0x24)
#define PERI_PCIE11_5116             (0x2C)
#define PERI_PCIE12_5116             (0x104)

#define PERI_PCIE1_0                 (0xEC)
#define PERI_PCIE1_1                 (0xF0)
#define PERI_PCIE1_6                 (0x104)
#define PERI_PCIE1_7                 (0x108)
#define PERI_PCIE1_8                 (0x10C)
#define PERI_PCIE1_9                 (0x110)

#define PCIE_SLV_DEVICE_TYPE         (28)
#define PCIE_SLV_DEVICE_TYPE_MASK    (0xF)

/*
 * special process for 5118 connected to QCA9880
 * when gpio68(boardid 1) is high, connected to QCA9880
 */
#define PCIE_SD5118_GPIO68           (68)
#define PCIE_SD5118_ULAR_REG         (0x2C)
#define PCIE_SD5118_ULAR_REG_VALUE   (0x10000)
#define PCIE_SD5118_EXP_ROM_BASE_REG (0x38)
#define PCIE_SD5118_EXP_ROM_VALUE1   (0x404100)
#define PCIE_SD5118_EXP_ROM_VALUE2   (0x8404100)
#define PCIE_SD5118_EXP_ROM_VALUE3   (0x100)
#define PCIE_SD5118_EXP_ROM_VALUE4   (0x42100)
#define PCIE_SD5118_EXP_ROM_VALUE5   (0x4042100)
#define PCIE_SD5118_EXP_ROM_VALUE6   (0x100)
#define PCIE_SD5118_EXP_ROM_VALUE7   (0x10000100)
#define PCIE_SD5118_EXP_ROM_VALUE8   (0x100)

/* forced pcie link mode */
#define PCIE_FORCE_LINK_1D1_MODE(value)    ((value | 0x1) & 0xFFFFFFF1)
#define PCIE_FORCE_LINK_2D0_MODE(value)    (value | 0x20000)
#define PCIE_1D1_LINK_MODE_REG_OFFSET      (0xa0)
#define PCIE_1D1_LINK_STATUS_MASK          (0x8020)
#define PCIE_1D1_LINK_STATUS               (0x8020)
#define PCIE_2D0_LINK_MODE_REG_OFFSET      (0x80c)
#define PCIE_2D0_LINK_STATUS_MASK          (0xFE0000)
#define PCIE_2D0_LINK_STATUS               (0x460000)
#define TRY_MAX_TIMES                      (100)
#define LINK_UP_STABLE_TIMES               (3)
#define PCIE_WORK_MODE_ENABLE              (0x40000000)

/* 5182T pcie link status mask */
#define PCIE_1D1_LINK_STATUS_MASK_5182T    (0x300)
#define PCIE_1D1_LINK_STATUS_5182T         (0x300)
#define PCIE_2D0_LINK_STATUS_MASK_5182T    (0xC3F)
#define PCIE_2D0_LINK_STATUS_5182T         (0x411)
#define PCIE_3D0_LINK_STATUS_MASK_5182T    (0xC3F)
#define PCIE_3D0_LINK_STATUS_5182T         (0x811)

/* PCIE bridge mode cfg */
#define PCIE_REG_SMBUS_TO_I2C(port, reg)   (port << 16 | reg << 8 | 0x8)
#define PCIE_SMBUS_DATA_LEN                (2)
#define PCIE_SMBUS_REG_ADDR_LEN            (1)
#define PCIE_SMBUS_DATA_INIT_VALUE         (0x8)
#define PCIE_SWITCH_PI7C9X2G304SL_DEV_ADDR (0x6f) /* bridge slave device addr */
#define PCIE_SWITCH_PI7C9X2G304SL_REG_LEN  (0x3)  /* bridge reg length */
#define PCIE_SWITCH_READ_TRY               (0xA)  /* smbus read try times */
#define PCIE_SWITCH_DOWN_PORT              (2)
#define PCIE_1D0_CMD_REG                   (0x8)
#define PCIE_1D0_CAPABILITY_REG            (0x8a)
#define PCIE_1D0_CFG_ENABLE_REG            (0xd0)

/* PCIE module clk reg */
#define PCIE_CLK_EN_REG          (0x148A0020)
#define PCIE_CLK_EN_REG2         (0x14880020)
#define PCIE_CLK_DIS_REG         (0x148A0024)
#define PCIE_CLK_DIS_REG2        (0x14880024)

/* PCIE module clk enable mask */
#define PCIE_CLK_EN_BIT12_MASK   (0x1000)
#define PCIE_CLK_EN_BIT13_MASK   (0x2000)
#define PCIE_CLK_EN_BIT14_MASK   (0x4000)
#define PCIE_CLK_EN_BIT15_MASK   (0x8000)
/* pcie module and WiFi ref clk */
#define PCIE_REF_CLK_EN_REG      (0x14880040)
/* pcie module and WiFi ref clk mask */
#define PCIE0_REF_CLK_EN_MASK    (0x77)
#define PCIE1_REF_CLK_EN_MASK    (0x770000)
#define PCIE1_5182H_REF_CLK_MASK (0x7700)

/* 5182T PCIE clk cfg mask */
#define PCIE0_CLK_EN_MASK_5182T  (0xF0000000)
#define PCIE1_CLK_EN_MASK_5182T  (0x0F000000)
#define PCIE2_CLK_EN_MASK_5182T  (0xF80)
#define PCIE3_CLK_EN_MASK_5182T  (0x1F000)
#define PCIE_APB_RST_REG_5182T   (0x148802E8)

/* 5182T PCIE module and WiFi ref clk mask */
#define PCIE0_REF_CLK_EN_MASK_5182T    (0x77000000)
#define PCIE1_REF_CLK_EN_MASK_5182T    (0x770000)
#define PCIE2_REF_CLK_EN_MASK_5182T    (0x77)
#define PCIE3_REF_CLK_EN_MASK_5182T    (0x7700)

/* peripherals reset reg */
#define PCIE_RST_CTRL0           (0x1488002C)
#define PCIE_RST_CTRL1           (0x14880034)
#define PCIE_RST_CTRL2           (0x148a0034)
#define PCIE_ACP_EN              (0x10100174)
#define PCIE_ACP_EN_1156         (0x10113180)

/* PCIE module reset enable mask */
#define PCIE_RST_PHY_BIT8_MASK   (0x100)
#define PCIE_RST_PHY_BIT9_MASK   (0x200)
#define PCIE_RST_PHY_BIT11_MASK  (0x800)
#define PCIE_RST_PHY_BIT12_MASK  (0x1000)
#define PCIE_RST_PHY_BIT14_MASK  (0x4000)
#define PCIE_RST_PHY_BIT18_MASK  (0x40000)

/* pcie system link init cfg */
#define PCIE_DIS_CTRL_VALUE1     (0x200000)
#define PCIE_DIS_CTRL_VALUE6     (0x8000000)
#define PCIE_WORK_MODE_VALUE     (0x40200000)
#define PCIE_EN_CTRL_VALUE7      (0x02200000)
#define PCIE_EN_CTRL_VALUE7_5182T      (0x20)

/* pcie gpio max drv ability */
#define PCIE_GPIO_MAX_ABILITY    (0X1C)

/* pcie delay para */
#define PCIE_UDELAY_1000         (1000)

/* MSI interrupt */
#define MAX_MSI_IRQS             (32)
#define MAX_MSI_CTRLS            (MAX_MSI_IRQS / 32)
#define DEFAULT_MSI_MAX_IRQS     (64)     /* max support 64 interrupt by default */

/* 5182T PCIE3 mode cfg reg */
#define PCIE3_MODE_REG_5182T     (0x14880124)

#define PCIE_COMMON_1D1_STATE_VALUE (0x440000)
#define PCIE_COMMON_2D_STATE_VALUE  (0x460000)
#define PCIE_5182T_1D1_STATE_VALUE  (0x311)
#define PCIE_5182T_2D_STATE_VALUE   (0x711)
#define PCIE_5182T_3D_STATE_VALUE   (0xB11)

#define PCIE_X2_MODE           (0)
#define PCIE_DOUBLE_X1_MODE    (1)
#define PCIE_X1_XFI_MODE       (0xa)

#define ADDR_SET(index) do { \
	alig_addr = (uint32_t *)(((uint32_t)g_pcie##index##_lb_test_buffer & \
		PCIE_LOOPBACK_BUFFER_ADDR_MASK) + PCIE_LOOPBACK_LTAR_OFFSET); \
	g_pcie##index##_iatu_table[IATU_INDEX_2].ltar = virt_to_phys(alig_addr); \
} while (0)

#define PCIE_ADDR_SET(index) do { \
	master_write_addr = (uint32_t *)g_pcie##index##_iatu_table[IATU_INDEX_2].lbar; \
	slave_write_addr = (uint32_t *) \
		(((uint32_t)g_pcie##index##_lb_test_buffer & \
		PCIE_LOOPBACK_BUFFER_ADDR_MASK) + \
		PCIE_LOOPBACK_LTAR_OFFSET); \
} while (0)

#define LINK_MODE_CHECK(index, version) \
	(((*feature_issupport)("HW_FT_AMP_PCIE"#index"_FORCE_PCIE"#version) == 1) && \
		(pcie_index == PCIE_INDEX_##index))

/* PCIE acp cfg */
enum pcie_acp_enable_config {
	PCIE_ACP_CLOSE = 1,
	PCIE_ACP_ENABLE = 2,

	PCIE_ACP_DEFAULE = 0xFF      /* keep default without change */
};

/* pcie swing dfx reg */
#define PCIE_SOC_DFX_CTRL_REG    (0x10100C1C)
#define PCIE_SWING_DFX_REG       (0x10100C10)

/* PCIE controller channel cross */
#define PCIE_CTRL_CHANNEL_CROSS_ON   (1)

/* pcie controller type */
enum pcie_ctrl_type {
	PCIE_CTRL_TYPE_NONE,
	PCIE_CTRL_TYPE_0,  /* controller 0 */
	PCIE_CTRL_TYPE_1,  /* controller 1 */
	PCIE_CTRL_TYPE_2,  /* controller 2 */

	PCIE_CTRL_TYPE_BUTT
};

enum pcie_force_link_type {
	PCIE_FORCE_LINK_DEFAULT = 0,
	PCIE_FORCE_LINK_10,
	PCIE_FORCE_LINK_11,
	PCIE_FORCE_LINK_20,

	PCIE_FORCE_LINK_BUTT
};

enum pcie_sel {
	pcie_sel_none,     /* neither controllers will be selected. */
	pcie0_x1_sel,      /* pcie0 selected. */
	pcie1_x1_sel,      /* pcie1 selected. */
	pcie2_x1_sel       /* pcie2 selected. */
};

enum pcie_work_mode {
	PCIE_WM_EP  = 0x0,  /* pci express endpoint device */
	PCIE_WM_LEP = 0x1,  /* legacy pci express endpoint device */
	PCIE_WM_RC  = 0x4   /* pci express root complex mode main mode */
};

/* PCIE iatu table index */
enum pcie_iatu_index {
	IATU_INDEX_0,
	IATU_INDEX_1,
	IATU_INDEX_2,
	IATU_INDEX_3,

	IATU_INDEX_MAX
};

/* PCIE interrupt mode */
enum pcie_interrupt_mode {
	PCIE_INTERRUPT_MODE_INTX = 0,
	PCIE_INTERRUPT_MODE_SMI,
	PCIE_INTERRUPT_MODE_SMIX,

	PCIE_INTERRUPT_MODE_BUTT
};

/* PCIE basic cfg */
struct pcie_basic_cfg {
	uint32_t pcie_link_force[PCIE_INDEX_MAX]; /* forced link mode 1.0/2.0 cfg */
	uint32_t pcie_work_mode[PCIE_INDEX_MAX];  /* pcie controller work mode */
};

/* PCIE controller */
struct pcie_info {
	int8_t root_bus_nr;            /* root bus number */
	enum pcie_ctrl_type controller;     /* belong to which controller */
	uint32_t base_addr;            /* device config space base addr & mem-io space base addr */
	uint32_t conf_base_addr;       /* rc config space base addr */
	uint32_t state;                /* link status */
	enum pcie_work_mode work_mode; /* work mode */

	/* add for SMI */
	uint32_t hardware_irq;

	void *__iomem misc_base;
	void *__iomem dbi_base;

	uint32_t stat0;
	uint32_t msi_irq;
	unsigned long msi_data;
	struct irq_domain *pcie_irq_domain;
	DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
	char irq_name[16];
	bool is_req_resource;
	struct pci_host_bridge *bridge;
};

/* PCIE module control data structure */
struct pcie_sys_ctrl {
	void *__iomem misc_base[PCIE_INDEX_MAX]; /* pcie mixed register base address */
	uint32_t controllers_num;                /* number of linked pcie devices */
	struct pcie_basic_cfg basic_cfg;         /* pcie baisc cfg */
	struct pcie_info info[PCIE_INDEX_MAX];   /* pcie status */
	struct pcie_board_ini_attr ext_cfg;      /* pcie extend cfg */
};

/* de-reset function for chip type selection */
struct pcie_undo_reset_select {
	enum HW_CHIP_ID_E chip_id;
	int32_t (*pf_pcie_undo_reset)(struct pcie_board_ini_attr *pcie_board_cfg, bool is_open);
};

/* reset function for chip type selection */
struct pcie_link_ops_reg {
	uint32_t is_5115_type;
	uint32_t dbi_base_addr[PCIE_INDEX_MAX];
	uint32_t ctrl_reg_0[PCIE_INDEX_MAX];
	uint32_t ctrl_reg_1[PCIE_INDEX_MAX];
	uint32_t ctrl_reg_6[PCIE_INDEX_MAX];
	uint32_t ctrl_reg_7[PCIE_INDEX_MAX];
	uint32_t ctrl_reg_8[PCIE_INDEX_MAX];
	uint32_t ctrl_reg_9[PCIE_INDEX_MAX];
	uint32_t link_state_reg[PCIE_INDEX_MAX];
	uint32_t link_2d0_reg[PCIE_INDEX_MAX];
};

struct reg_cfg {
	uint32_t reg;
	uint32_t value;
};

struct pcie_clk_reg {
	uint32_t chip_id;
	struct reg_cfg clk_cfg[PCIE_INDEX_MAX];
	struct reg_cfg ref_clk[PCIE_INDEX_MAX];
};

struct pcie_rest_phy_reg {
	uint32_t chip_id;
	struct reg_cfg rst_ctrl[PCIE_INDEX_MAX];
};

struct pcie_iatu {
	uint32_t viewport;      /* iATU Viewport Register */
	uint32_t region_ctrl_1; /* Region Control 1 Register */
	uint32_t region_ctrl_2; /* Region Control 2 Register */
	uint32_t lbar;          /* Lower Base Address Register */
	uint32_t ubar;          /* Upper Base Address Register */
	uint32_t lar;           /* Limit Address Register */
	uint32_t ltar;          /* Lower Target Address Register */
	uint32_t utar;          /* Upper Target Address Register */
};

/* PCIE init list */
struct pcie_reg_op {
	uint32_t addr;
	uint32_t mask;
	uint32_t val;
};

/* pci cfg */
struct pcie_reg_base_addr {
	uint32_t dbi_base_addr;         /* pcie dbi(Data Bus Inversion) space base addr */
	uint32_t misc_base_addr;        /* pcie misc reg base addr */
	uint32_t link_status_reg;       /* pcie link status reg */
	uint32_t link_2d0_status_reg;   /* pcie2.0 link status reg */
	uint32_t mem_base_addr;         /* pcie devices mem space base addr */
	uint32_t cfg_base_addr;         /* pcie devices cfgspace base addr */
	uint32_t mem_base_size;         /* pcie devices mem space mapping size */
	uint32_t cfg_base_size;         /* pcie devices cfg space mapping size */
	uint32_t pcie_msi_irq_num;      /* pcie msi interrupt id */
	uint32_t reg_op_list_num;       /* pcie init list num */
	struct pcie_reg_op *reg_op_list;       /* pcie init list */
};

extern enum HW_CHIP_ID_E hw_kernel_get_chip_id(void);

/* declaration for enternal invoking */
int32_t clear_reg_iomap_bit(uint32_t addr, uint32_t bit);
int32_t clear_reg_iomap_mask(uint32_t addr, uint32_t mask);
int32_t clear_reg_iomap_mask_set_val(uint32_t addr, uint32_t mask, uint32_t val);
int32_t set_reg_iomap_bit(uint32_t addr, uint32_t bit);
int32_t write_reg_iomap_value(uint32_t addr, uint32_t value);
int32_t read_reg_iomap_value(uint32_t addr, uint32_t *value);
void orr_reg_value(void *__iomem reg_addr, uint32_t value);
void clear_reg_mask(void *__iomem reg_addr, uint32_t mask);
void clear_reg_bit(void *__iomem reg_addr, uint32_t bit);
void set_reg_bit(void *__iomem reg_addr, uint32_t bit);
int32_t set_gpio_dir_output(uint32_t gpio_num);
int32_t set_gpio_output_value(uint32_t gpio_num, uint32_t value);
int32_t set_gpio_drv_ability(uint32_t gpio_num, uint32_t ability);
void pcie_undo_ioremap(void);
enum HW_CHIP_ID_E pcie_get_chip_id(void);
uint32_t pcie_loopback_test(void *pcie_test_data);
void pcie_set_iatu_table(struct pcie_iatu *pcie0_iatu,
	struct pcie_iatu *pcie1_iatu, struct pcie_iatu *pcie2_iatu);
void pcie_set_iatu_table_len(uint32_t pcie0_len, uint32_t pcie1_len, uint32_t pcie2_len);
void pcie_get_misc_base_virt(uint32_t index, void **__iomem pcie_misc_base);
void pcie_set_misc_base_virt(uint32_t index, void *__iomem pcie_misc_base);
void pcie_get_ctrl_info(struct pcie_info **pcie_ctrl);
void disable_l2cache_outer(void);
void pcie_bridge_config_pcie10(void);
void pcie_enable_clk(uint32_t pcie_id);
void pcie_clk_poweroff(uint32_t pcie_id);
int32_t pcie_ctrl_init(uint32_t pcie_index, uint32_t cfg_size,
	uint32_t mem_size, uint32_t *controllers_nr);
uint32_t pcie_hisi_sys_init(uint32_t pcie_index, struct pcie_link_ops_reg link_ops);
void pcie_dev_force_close(void);
struct pcie_info *get_pcie_info_by_index(uint32_t index);
bool pcie_get_linkup_status(uint32_t pcie_index);
void *pcie_get_dbi_addr(uint32_t pcie_index);
int32_t set_reg_iomap_mask(uint32_t addr, uint32_t mask);
int32_t pcie_check_link_mode(uint32_t pcie_index, struct pcie_link_ops_reg link_ops,
	void *__iomem dbi_base_addr);
uint32_t pcie_aging_loopback_check(void);
void pcie_aging_loopback_test(uint32_t chipid);
void hi_pcie_post_config(uint32_t port);
uint32_t pcie_chip_link_speed_info_get(struct pcie_link_state_info *info,
	uint32_t info_size, uint32_t *pcie_num);
void pcie_clk_power_exit(void);
#endif /* PCIE_CHIP_H */
